The present invention relates to semiconductor devices and more particularly to a process for fabricating polysilicon resistors for use in integrated circuits including Field Effect Transistor (FET) devices.
Heretofore, in the case of Complementary Metal Insulator Semiconductor (CMIS) Complementary Metal Oxide Semiconductor (CMOS) (FET) technology, it has been typical for the gate electrode stack of a Metal Oxide (MOS) FET device to comprise a conductor in the form of a doped polysilicon gate electrode formed over a gate dielectric layer composed of a dielectric material such as silicon oxide. A disadvantage of utilizing polysilicon gates is that at inversion, polysilicon gate electrodes generally experience depletion of carriers in the area of the polysilicon gate adjacent to the gate dielectric. Such depletion of carriers, which is referred to in the art as the polysilicon depletion effect, reduces the effective gate capacitance of the Metal Insulator Semiconductor (MIS) device. More recently MIS FET devices have substituted high-K gate dielectric materials for the materials such as silicon oxide of MOS FET devices and metal gates have been substituted for polysilicon or combined therewith. Thus a gate electrode stack may comprise a complex stack of high K dielectric material, a metal layer, a layer of doped polysilicon, and a silicide layer. In CMOS devices including a gate stack comprising a bottom polysilicon portion and a top silicide portion a layer of silicide in such a gate stack contributes to a decrease in the resistance of the gate. The decrease in resistance causes a decrease in the time propagation delay RC of the gate. Although a silicide top gate region may help to decrease the resistance of the transistor, charge is still depleted in the vicinity of the interface formed between the bottom polysilicon gate and gate dielectric, thereby causing a smaller effective gate capacitance.
Commonly assigned copending U.S. Patent Application No. 2007/0148838 of Doris et al. entitled “Metal Gate CMOS with at Least a Single Gate Metal and Dual Gate Dielectrics” states that in one type of “CMOS device the gate electrode includes at least a metal layer beneath a Si-containing, e.g., polysilicon, gate electrode.”
Typical resistor processing provides for a doped polysilicon resistor body, where a block layer is employed to exclude the low resistance silicidation from the resistor body. This approach can have drawbacks due to the multiple process steps that influence the resistance value, and thus increase resistor tolerance.
An alternative to employing a doped polysilicon resistor body, where a block layer is employed to exclude the low resistance silicidation from the resistor body is to utilize a separately processed resistor layer, for instance in the (Back End Of the Line) BEOL processing of the device. This adds significant process costs to the technology due to additional deposition, lithography and etching steps.
U.S. Pat. No. 6,462,386 of Moriwaki et al. entitled “Semiconductor Device and Method of Manufacturing the Same” describes a semiconductor device comprising a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate with a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and over on the second gate insulating film.
U.S. Pat. No. 7,112,535 of Coolbaugh et al. entitled “Precision Polysilicon Resistor Process” which is commonly assigned describes a process for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process includes performing an emitter/FET activation Rapid Thermal Anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide. The process included forming a first gate insulating film, having a relatively large thickness, on a semiconductor substrate followed by forming thereon a first gate electrode composed of a polysilicon film. A second FET includes a second gate insulating film formed on the semiconductor substrate which has a relatively small thickness; and forming thereon a second gate electrode composed of a metal film, and a barrier metal covering the sides and bottom of the first gate electrode formed in between the second gate insulating film and the second gate electrode. A resistor is composed of a polysilicon film formed in the step of forming the polysilicon film of the first gate electrode.